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What just happened? It’s been a long wait, but we’re finally getting our first in-depth look at AMD’s next-gen Zen 5 processor architecture. Earlier this month at Computex, AMD gave us a high-level overview of their latest CPU design, and now some juicy technical details are starting to emerge, courtesy of David Huang, a blogger who managed to get his hands on an engineering sample laptop powered by one of AMD’s new Strix Point APUs.

The laptop Huang tested was powered by the Ryzen AI 9 365. This chip is set to launch next month alongside the higher-end Ryzen AI 9 370. There’s quite a bit to digest here as the new architecture introduces plenty of changes. The headliner is an innovative new hybrid design that pairs higher-performance “Zen 5” cores with more efficient “Zen 5c” cores on a single chip.

The Zen 5 cores remain the heavyweight performers, with higher clocks and more cache. But the Zen 5c cores should handle lighter workloads more efficiently. In the laptop chip Huang tested, there were 4 beefy Zen 5 cores and 6 smaller Zen 5c cores. Desktop chips will likely have a different core combination.

One of the most interesting revelations is how AMD has mixed things up on the cache front for these mobile chips. Instead of giving all cores an equal slice of the L3 pie, the four standard Zen 5 cores get a hefty 16MB portion while the six Zen 5c cores have to make do with just 8MB. It’s an unorthodox approach, but one that could allow AMD to strike a solid balance between performance and efficiency.

Pre-launch testing of Ryzen AI Zen 5 APU confirms AMD’s IPC claims

AMD has also redesigned the front end to enable higher instruction throughput, with the ability to fetch and decode more operations in parallel. The branch prediction capabilities have also been enhanced.

On the execution side, Zen 5 widens its lead in scalar performance, but there are some trade-offs with SIMD/vector workloads. Integer SIMD throughput has taken a hit on the Zen 5 cores, with 128/256-bit operations running about half the speed of Zen 4. This shortcoming, Huang notes, could be deliberate to maintain high frequencies. But 512-bit vector operations remain unchanged.

Pre-launch testing of Ryzen AI Zen 5 APU confirms AMD’s IPC claims

As for benchmarks, locking the classic cores to 4.8 GHz showed a 22% performance uplift for Zen 5 over Zen 4, attributable to an estimated 9.7% IPC gain. Geekbench testing aligned with AMD’s projections, indicating 15 – 17.6% IPC improvements with the Zen 5 architecture compared to its predecessor. The actual performance tests are rather comprehensive (and technical) so if you wish to go through them, check out his blog.

However, Huang summarized that neither the performance nor efficiency cores offer the “best performance.” He attributes these to cutbacks in cache size, SIMD capabilities, and operating frequencies. Just keep in mind that these tests weren’t run on consumer-ready silicon, so take the specifics with a grain of salt.

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